Bit synchronization to a digital transmission is a process used to determine the presence of symbol boundaries of a data transmission and thereafter to optionally provide a bit clock to synchronously sample data bits, or data symbols from the data transmission. Bit synchronization may be a process used in a selective call receiver decoding a digital signaling protocol, for example, that proposed by British Telecom in England which is commonly termed POCSAG (Post Office Code Standardization Advisory Group).
Synchronization to such a protocol is known and has been described in detail in U.S. Pat. No. 4,518,961 which shows synchronization to either the POCSAG or a Golay signalling protocols. Additionally, U.S. Pat. No. 4,506,262 shows syncrhonization to POCSAG using an early/late phase locked loop with course and fine synchronization modes.
Referring to FIG. 1, line 10 comprises a typical POCSAG signal. Prior to the signal, noise or another type of protocol may be transmitted as shown in area 12 enclosed in a broken line. The POCSAG signal begins with a preamble signal, 14, which comprises a number of one-zero transitions. The preamble is followed by a plurality of thirty two bit information words, each coded in a 31, 21 extended BCH code (32, 21). The information words begin with a sync code word 16a which contains predetermined binary sequence. Every seventeenth word thereafter another sync code 16b occurs in the signal. Between the sync codes, the information is structured as eight information frames each of which comprises two 32, 21 words. For illustration, the contents of frame 4, as indicated by the number 18, is shown on line 34. Line 34 has two 32 bit words, 36 and 38, each information word having 32 data bits structured in the 32, 21 format. It can be appreciated that the data bits shown on line 34 can appear to be effectively a random sequence.
The sync code provides a means for frame synchronization to the signal. Thus it is desirable to first bit synchronize to the preamble signal and subsequently frame synchronize to the sync code. Line 20 shows the operation of a selective call receiver synchronizing to the POCSAG signal. During interval 22 and 24, the selective call receiver is attempting to synchronize to the signal. However, the signal is not present. During interval 26, the preamble signal, 14, is present, the selective call receiver bit synchronizes and finds sync code 16a. Then in a known manner, the selective call receiver decodes information in preassigned frame 4 as shown by intervals 28 and 32. The selective call receiver also tests for sync code 16b during interval 30 in order to determine the continued presence of the transmission.
In some instances, the preamble signal may be corrupted by noise rendering the preamble signal undetectable. In this situation, it is desirable to acquire bit synchronization on the data bits within the thirty two bit words, and subsequently frame synchronize to one of the periodic sync code signals. The bit synchronization process in this mode is more difficult because the data in the thirty two bit words is effectively random. Consequently, it is desirable to provide a selective call receiver capable of acquiring bit synchronization on either a POCSAG preamble signal or data signals within POCSAG information words.
Battery life is a critical aspect of portable selective call receivers and it is desirable to conserve battery power whenever possible. In the absence of the POCSAG signal, selective call receivers operate in a low power mode and periodically activate receiving and decoding circuitry in order to detect the presence of the POCSAG signal. If no signal is detected, the selective call receiver again operates in a low power mode. This process conserves battery power. Thus it is desirable to quickly detect the absence of the signal in order to hasten the return to the low power mode.
Prior art selective call receivers have typically analyzed a predetermined number of transitions and in response to various algorithms determine the absence of the POCSAG signal. One such algorithm is shown in U.S. Pat. No. 4,554,665 wherein the using of a predetermined number of transitions requires waiting for all of the transitions to occur. Such techniques suffer greatly under conditions where transitions occur relatively infrequently, such as when low frequency tones are transmitted in place of the POCSAG signal. While waiting for all of the transitions to occur, the prior art receivers are consuming additional battery power.
Furthermore, prior art selective call receivers typically establish a predetermined relationship between the sensitivity of detecting the POCSAG signal in a noise environment and falsely detecting a POCSAG signal when only noise or another signal is present. Since upon the detection of the absence of a POCSAG signal, power is conserved by deactivating the receiver, this establishment results in a certain average battery power consumption while searching for signal. However because selective call receivers are used in many different selective call receiver environments around the world, a sensitivity and falsing and battery power consumption performance in one application may not be optimal for another application.
Yet further, a recent version of the POCSAG signal has a 1200 baud data rate. Typical bit synchronizers capable of synchronizing to a data transmission having random data at 1200 baud will also synchronize to data transmissions being an integer divisor of that data rate (600, 300 baud). For example, the Golay Sequential Code (GSC) is another selective call receiver protocol which transmits message information at 600 and 300 baud.
Additionally, prior art selective call receivers with microcomputers typically sample the incoming signal at a very high rate, and typically use a digital phase locked loop implemented in software in order to establish a bit clock for sampling data bits after synchronization. Software generated digital phase locked loops require high sampling rates and continuous phase adjustments in a real time software environment. This requires a microcomputer to operate at a relative high bus rate. U.S. Pat. No. 4,414,676 shows a synchronizer which samples at five times the data rate and performs numerous calculations between each sample; however, it does not show the capability to synchronize on random data.